november 2013 fqd1n60c / fqu1n60c ? n-channel qfet ? mosfet ?2003 fairchild semiconductor corporation fqd1n60c / fqu1n60c rev. c1 www.fairchildsemi.com 1 absolute maximum ratings t c = 25c unless otherwise noted. thermal characteristics symbol parameter FQD1N60CTM / fqu1n60ctu unit v dss drain-source voltage 600 v i d drain current - continuous (t c = 25c) 1a - continuous (t c = 100c) 0.6 a i dm drain current - pulsed (note 1) 4a v gss gate-source voltage 30 v e as single pulsed avalanche energy (note 2) 33 mj i ar avalanche current (note 1) 1a e ar repetitive avalanche energy (note 1) 2.8 mj dv/dt peak diode recovery dv/dt (note 3) 4.5 v/ns p d power dissipation (t a = 25c)* 2.5 w power dissipation (t c = 25c) 28 w - derate above 25c 0.22 w/c t j , t stg operating and storage temperature range -55 to +150 c t l maximum lead temperature for soldering purposes, 1/8 " from case for 5 seconds 300 c symbol parameter FQD1N60CTM / fqu1n60ctu unit r jc thermal resistance, junction-to-case, max. 4.53 c / w r ja thermal resistance, junction-to-ambient (minimum pad of 2 oz copper), max. 110 thermal resistance, junction-to-ambient (* 1 in 2 pad of 2 oz copper), max. 50 fqd1n60c / fqu1n60c n-channel qfet ? mosfet 600 v, 1.0 a, 11.5 ? features ? 1 a, 600 v, r ds(on) = 11.5 ? (max.) @ v gs = 10 v, i d = 0.5 a ? low gate charge (typ. 4.8 nc) ? low crss (typ. 3.5 pf) ? 100% avalanche tested ? rohs compliant description this n-channel enhancement mode power mosfet is produced using fairchild semiconductor?s proprietary planar stripe and dmos te chnology. this advanced mosfet technology has been es pecially tailored to reduce on-state resistance, and to provide superior switching performance and high avalanche energy strength. these devices are suitable for switched mode power supplies, active power factor correction (pfc), and electronic lamp ballasts. g d s i-pak d-pak g s d g s d
fqd1n60c / fqu1n60c ? n-channel qfet ? mosfet ?2003 fairchild semiconductor corporation fqd1n60c / fqu1n60c rev. c1 www.fairchildsemi.com 2 package marking and ordering information electrical characteristics t c = 25c unless otherwise noted. notes: 1. repetitive rating : pulse width limited by maximum junction temperature. 2. l = 59 mh, i as = 1.1 a, v dd = 50 v, r g = 25 , starting t j = 25c. 3. i sd 1.1 a, di/dt 200 a/ s, v dd bv dss, starting t j = 25c. 4. essentially independent of operating temperature. device marking device package reel size tape width quantity fqd1n60c FQD1N60CTM d-pak 330mm 16mm 2500 units fqu1n60c fqu1n60ctu i-pak tube n/a 70 units symbol parameter test conditions min typ max unit off characteristics bv dss drain-source breakdown voltage v gs = 0 v, i d = 250 a 600 -- -- v bv dss / t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25c -- 0.6 -- v/c i dss zero gate voltage drain current v ds = 600 v, v gs = 0 v -- -- 1 a v ds = 480 v, t c = 125c -- -- 10 a i gssf gate-body leakage current, forward v gs = 30 v, v ds = 0 v -- -- 100 na i gssr gate-body leakage current, reverse v gs = -30 v, v ds = 0 v -- -- -100 na on characteristics v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 2.0 -- 4.0 v r ds(on) static drain-source on-resistance v gs = 10 v, i d = 0.5 a -- 2.8 3.4 g fs forward transconductance v ds = 40 v, i d = 0.5 a -- 3.5 -- s dynamic characteristics c iss input capacitance v ds = 25 v, v gs = 0 v, f = 1.0 mhz -- 130 170 pf c oss output capacitance -- 19 25 pf c rss reverse transfer capacitance -- 3.5 4.5 pf switching characteristics t d(on) turn-on delay time v dd = 300 v, i d = 1.1 a, r g = 25 (note 4) -- 7 24 ns t r turn-on rise time -- 21 52 ns t d(off) turn-off delay time -- 13 36 ns t f turn-off fall time -- 27 64 ns q g total gate charge v ds = 480 v, i d = 1.1 a, v gs = 10 v (note 4) -- 4.8 6.2 nc q gs gate-source charge -- 0.7 -- nc q gd gate-drain charge -- 2.7 -- nc drain-source diode characteristics and maximum ratings i s maximum continuous drain-source diode forward current -- -- 1 a i sm maximum pulsed drain-source diode forward current -- -- 4 a v sd drain-source diode forward voltage v gs = 0 v, i s = 0.5 a -- -- 1.4 v t rr reverse recovery time v gs = 0 v, i s = 1.1 a, di f / dt = 100 a/ s -- 190 -- ns q rr reverse recovery charge -- 0.53 -- c
fqd1n60c / fqu1n60c ? n-channel qfet ? mosfet ?2003 fairchild semiconductor corporation fqd1n60c / fqu1n60c rev. c1 www.fairchildsemi.com 3 typical performance characteristics figure 1. on-region characteristics figure 2. transfer characteristics figure 3. on-resistance variation vs. figure 4. body diode forward voltage drain current and gate voltage v ariation vs. s ource current and temperature figure 5. capacitance characteristics figure 6. gate charge characteristics 10 0 10 1 10 -1 10 0 10 1 v gs top : 15.0 v 10.0 v 8.0 v 7.0 v 6.5 v 6.0 v 5.5 v bottom : 5.0 v notes : 1. 250 s pulse test 2. t c = 25 i d , drain current [a] v ds , drain-source voltage [v] 246810 10 0 10 1 150 o c 25 o c -55 o c notes : 1. v ds = 40v 2. 250 s pulse test i d , drain current [a] v gs , gate-source voltage [v] 01234567 0 2 4 6 8 10 12 v gs = 20v v gs = 10v note : t j = 25 r ds(on) [ ? ], drain-source on-resistance i d , drain current [a] 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 10 -1 10 0 10 1 150 notes : 1. v gs = 0v 2. 250 s pulse test 25 i dr , reverse drain current [a] v sd , source-drain voltage [v] 10 -1 10 0 10 1 0 100 200 300 400 500 600 700 800 c iss = c gs + c gd (c ds = shorted) c oss = c ds + c gd c rss = c gd note ; 1. v gs = 0 v 2. f = 1 mhz c rss c oss c iss capacitances [pf] v ds , drain-source voltage [v] 024681012 0 2 4 6 8 10 12 v ds = 300v v ds = 120v v ds = 480v note : i d = 10a v gs , gate-source voltage [v] q g , total gate charge [nc]
fqd1n60c / fqu1n60c ? n-channel qfet ? mosfet ?2003 fairchild semiconductor corporation fqd1n60c / fqu1n60c rev. c1 www.fairchildsemi.com 4 typical characteristics (continued) figure 9. maximum safe operating area figure 10. maximum drain current vs case temperature -100 -50 0 50 100 150 200 0.8 0.9 1.0 1.1 1.2 notes : 1. v gs = 0 v 2. i d = 250 a bv dss , (normalized) drain-source breakdown voltage t j , junction temperature [ o c] -100 -50 0 50 100 150 200 0.0 0.5 1.0 1.5 2.0 2.5 3.0 notes : 1. v gs = 10 v 2. i d = 0.5 a r ds(on) , (normalized) drain-source on-resistance t j , junction temperature [ o c] figure 11. transient thermal response curve 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 -1 10 0 notes : 1. z jc (t) = 4.53 /w max. 2. d uty factor, d =t 1 /t 2 3. t jm - t c = p dm * z jc (t) single pulse d=0.5 0.02 0.2 0.05 0.1 0.01 z jc (t), thermal response t 1 , square w ave pulse duration [sec] t 1 p dm t 2 10 0 10 1 10 2 10 3 10 -2 10 -1 10 0 10 1 10 ms dc 100 ms 1 ms 100 s operation in this area is limited by r ds(on) notes : 1. t c = 25 o c 2. t j = 150 o c 3. single pulse i d , drain current [a] v ds , drain-source voltage [v] 25 50 75 100 125 150 0.0 0.2 0.4 0.6 0.8 1.0 1.2 i d , drain current [a] t c , case temperature [ ] figure 7. breakdown voltage variation vs temperature figure 8. on-resistance variation vs temperature z jc (t), thermal response [ o c/w]
fqd1n60c / fqu1n60c ? n-channel qfet ? mosfet ?2003 fairchild semiconductor corporation fqd1n60c / fqu1n60c rev. c1 www.fairchildsemi.com 5 figure 12. gate charge test circuit & waveform figure 13. resistive switching test circuit & waveforms figure 14. unclamped inductive switching test circuit & waveforms v gs v ds 10% 90% t d(on) t r t on t off t d(off) t f v dd 10v v ds r l dut r g v gs v gs v ds 10% 90% t d(on) t r t on t off t d(off) t f v dd 10v v ds r l dut r g v gs v gs charge v gs 10v q g q gs q gd 3ma v gs dut v ds 300nf 50k 200nf 12v same type as dut charge v gs 10v q g q gs q gd 3ma v gs dut v ds 300nf 50k 200nf 12v same type as dut e as =li as 2 ---- 2 1 -------------------- bv dss -v dd bv dss v dd v ds bv dss t p v dd i as v ds (t) i d (t) time 10v dut r g l i d t p e as =li as 2 ---- 2 1 e as =li as 2 ---- 2 1 ---- 2 1 -------------------- bv dss -v dd bv dss v dd v ds bv dss t p v dd i as v ds (t) i d (t) time 10v dut r g l l i d i d t p v gs v gs i g = const.
fqd1n60c / fqu1n60c ? n-channel qfet ? mosfet ?2003 fairchild semiconductor corporation fqd1n60c / fqu1n60c rev. c1 www.fairchildsemi.com 6 figure 15. peak diode recovery dv/dt test circuit & waveforms dut v ds + _ driver r g same type as dut v gs ? dv/dt controlled by r g ?i sd controlled by pulse period v dd l i sd 10v v gs ( driver ) i sd ( dut ) v ds ( dut ) v dd body diode forward voltage drop v sd i fm , body diode forward current body diode reverse current i rm body diode recovery dv/dt di/dt d = gate pulse width gate pulse period -------------------------- dut v ds + _ driver r g same type as dut v gs ? dv/dt controlled by r g ?i sd controlled by pulse period v dd l l i sd 10v v gs ( driver ) i sd ( dut ) v ds ( dut ) v dd body diode forward voltage drop v sd i fm , body diode forward current body diode reverse current i rm body diode recovery dv/dt di/dt d = gate pulse width gate pulse period -------------------------- d = gate pulse width gate pulse period --------------------------
fqd1n60c / fqu1n60c ? n-channel qfet ? mosfet ?2003 fairchild semiconductor corporation fqd1n60c / fqu1n60c rev. c1 www.fairchildsemi.com 7 mechanical dimensions dimension in millimeters to-252 3l (dpak) figure 16. to252 (d-pak), molded, 3 lead, option aa&ab package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the draw ing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specif- ically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packag ing area for the most recent package drawings: http://www.fairchildsemi.com/package/packagedetails.html?id=pn_tt252-003
fqd1n60c / fqu1n60c ? n-channel qfet ? mosfet ?2003 fairchild semiconductor corporation fqd1n60c / fqu1n60c rev. c1 www.fairchildsemi.com 8 mechanical dimensions dimension in millimeters to-251 3l (ipak) figure 17. to251 (ipak) molded 3 lead package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the draw ing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specif- ically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packag ing area for the most recent package drawings: http://www.fairchildsemi.com/package/packagedetails.html?id=pn_to251-003
fqd1n60c / fqu1n60c ? n-channel qfet ? mosfet ?2003 fairchild semiconductor corporation fqd1n60c / fqu1n60c rev. c1 www.fairchildsemi.com 9 trademarks the following includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. *trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or desi gn. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s worldwide terms and conditio ns, specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized for use as critical components in life support de vices or systems without the express written approval of fai rchild semiconductor corporation. as used here in: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms accupower? 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